As a technology in the field of the non-volatile memories and on-chip memories examined by the inventors of the present invention, for example, the following technologies are known.
In order to attain high-speed and highly-integrated non-volatile memories, phase change memories are being developed. The phase change memories are disclosed in Japanese Patent Application Laid-Open Publication No. 2003-100084 (Patent Document 1), the specification of U.S. Pat. No. 6,625,054 (Patent Document 2), “IEEE International Solid-State Circuits Conference, Digest of Technical Papers)”, U.S., 2002, pp. 202-203 (Non-patent Document 1), “IEEE International Electron Devices Meeting, Technical Digest” U.S., 2002, pp. 923-926 (Non-patent Document 2), and “Non-Volatile Semiconductor Memory Workshop, Digest of Technical Papers)”, U.S., 2003, pp. 91-92 (Non-patent Document 3). As described in Non-patent Document 1, for example, in a phase change memory, information is stored by utilizing that resistance of a phase change material called chalcogenide varies depending on the state thereof. The rewriting of the phase change resistor is performed by changing the state of the phase change resistor in such a manner that an electric current is allowed to flow so as to generate a heat. The resistance increase (change into amorphous (non-crystalline) state) which is also called also as a reset operation (RESET) is performed in a state where a comparatively high temperature is maintained, and the resistance decrease (change into crystalline state) which is also called as a set operation (SET) is performed in a state where a comparatively low temperature is maintained for a sufficient period. A read operation for the phase change material is performed in such a manner that an electric current is allowed to flow within a range that does not change the state of the phase change resistor.
Non-patent Document 2 and Patent Document 1 describe the characteristics of the phase change resistor. Further, Non-patent Document 3 describes a memory cell, which is composed of phase change resistor and an n channel MOS (Metal Oxide Semiconductor) transistor. Patent Document 2 describes multi-bit operation of a phase change memory.
These documents describe not only a high-speed ROM (Read-Only Memory) but also possibility of a non-volatile RAM (Random Access Memory), and they also mention the realization of a unified memory having the functions of both ROM and RAM. Since the phase of the phase change resistor can be changed by a lower electric power in the phase change memory having smaller electrode area of the phase change resistor, scaling is facilitated. Further, since the phase change resistor changes greatly, a high-speed read operation can be realized. Also, the multi-bit operation is possible and thus high integration can be realized. For these reasons, the realization of a high-speed non-volatile memory by the phase change memory is expected.